The present disclosure relates generally to the electrical, electronic and computer arts and, more particularly, to inverters including vertical field-effect transistors (VFETs) and their fabrication.
With shrinking dimensions of various integrated circuit components, transistors such as FETs have experienced dramatic improvements in both performance and power consumption. These improvements may be largely attributed to the reduction in dimensions of components used therein, which in general translate into reduced capacitance, resistance, and increased through-put current from the transistors. Metal oxide semiconductor field-effect transistors (MOSFETs) are well suited for use in high-density integrated circuits.
CMOS inverter circuits including two MOSFETs, one being a pMOS FET, the other being an nMOS FET, have been developed. In such inverter circuits, both gates are electrically connected to an input line. The source of the NFET is tied to Vss (the low voltage power supply, for example ground). The source of the PFET is connected to Vdd (the high voltage power supply). Vout is electrically connected to the drain terminals. The inverter input controls both transistors simultaneously.
Vertical field-effect transistors (VFETs) have configurations wherein the current between the drain and source regions is substantially normal to the surface of the die. A vertical field-effect transistor may include semiconductor pillar having top and base regions comprising source/drain regions, the portion of the pillar between the source/drain regions defining a channel region.